The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a non-volatile semiconductor memory device such as a flash electrically erasable programmable read only memory.
A floating gate field effect transistor serves as a non-volatile semiconductor memory device which is capable of electrically erasing and programming informations. The floating gate field effect transistor has recently be used as the flash electrically erasable programmable read only memory. The floating gate field effect transistor serving as the flash electrically erasable programmable read only memory has the following structure. Source and drain regions are selectively formed in an upper region of a semiconductor substrate, so that the source and drain regions are separated by a channel region of the semiconductor substrate, whereby the channel region is defined between the source and drain regions. A first gate insulation film is formed on the channel region. A floating gate electrode is provided on the first gate insulation film. A second gate insulation film is provided on a top surface of the floating gate electrode. A control gate electrode is provided on the second gate insulation film.
Usually, the first gate insulation film comprises a single layered structure of a silicon oxide film formed on a main face of the semiconductor substrate, whilst the second gate insulation film comprises a double layered structure of a silicon oxide film and a silicon nitride film.
Information data are stored in the floating gate, wherein charges are accumulated or stored in the floating gate. The information data are written into the floating gate by injecting electrons from the substrate to the floating gate. The information data are erased from the floating gate by discharging electrons from the floating gate to the substrate. The accumulation of electrons or charges in the floating gate changes the threshold voltage of the floating gate field effect transistor. Namely, the threshold voltage of the floating gate field effect transistor is switched between different levels, for example, two levels depending upon the accumulation or discharge of electrons or charges in the floating gate. If the threshold voltage is switched between two levels, then binary digit data are stored in the floating gate.
FIG. 1 is a fragmentary cross sectional elevation view illustrative of a conventional floating gate field effect transistor serving as a flash electrically erasable programmable read only memory. N-type source and drain regions 106 and 107 are selectively provided in an upper region of a p-type silicon substrate 101, so that the n-type source and drain regions 106 and 107 are separated by a channel region of the p-type silicon substrate 101, whereby the channel region is defined between the n-type source and drain regions 106 and 107. A first gate insulation film 102 is provided on the channel region. A floating gate electrode 103 is provided on the first gate insulation film 102. A second gate insulation film 104 is provided on a top surface of the floating gate electrode 103. A control gate electrode 105 is provided on the second gate insulation film 104.
FIG. 2A is a fragmentary schematic cross sectional elevation view illustrate of an erasing operation of the conventional floating gate field effect transistor serving as a flash electrically erasable programmable read only memory shown in FIG. 1. FIG. 2B is a fragmentary schematic cross sectional elevation view illustrate of a writing operation of the conventional floating gate field effect transistor serving as a flash electrically erasable programmable read only memory shown in FIG. 1. FIG. 2C is a fragmentary schematic cross sectional elevation view illustrate of a read out operation of the conventional floating gate field effect transistor serving as a flash electrically erasable programmable read only memory shown in FIG. 1. FIG. 3 is a diagram illustrative of variations of a cumulative degree over threshold voltage of a low threshold voltage transistor and a high threshold voltage transistor.
With reference to FIG. 2A, the erasure operation of the floating gate field effect transistor will be described. A control voltage Vg of the control gate electrode 105 is fixed at about xe2x88x9220V. A substrate voltage of the substrate 101 is fixed at the ground potential. Electrons are discharged from the floating gate electrode 103 and travel as a Fowler Nordheim tunnel current through the first gate insulation film 102 to the substrate 101. During the erasure operation, the source and drain regions 106 and 107 remain in the floating state. As shown in FIG. 3, the floating gate field effect transistor during the erasure operation may be considered to be a low threshold voltage floating gate field effect transistor having a low threshold voltage of about 1-2V. In FIG. 3, a few times verifying operations are carried out for the electron discharge from the floating gate electrode 103. This verifying operation is like that if any excess discharge of electrons from the floating gate electrode is caused, then electrons are injected into the floating gate electrode so as to adjust or control the amount of electrons in the floating gate electrode, thereby to reduce a variation in threshold voltage of the floating gate field effect transistor.
The write operation of the above conventional floating gate field effect transistor will be described with reference to FIG. 2B. A source voltage Vs of the source region 106 is fixed at the ground potential. A drain voltage Vd of the drain region 107 is fixed at a plus potential. A control gate electrode 105 is applied with a high voltage Vg to form an n-channel between the source and drain regions 106 and 107, whereby electrons as carriers flow from the source region 106 through the n-channel to the drain region 107. Since the high voltage Vg applied to the control gate electrode 105 is higher than the drain voltage Vd of the drain region 107, the potential of the floating gate electrode 103 is an intermediate level between the high voltage Vg applied to the control gate electrode 105 and the drain voltage Vd of the drain region 107, whereby an electric field is applied across the first gate insulation film 102 between the floating gate electrode 103 and the drain region 107. As a result, the electrons penetrate the first gate insulation film 102 and are injected into the floating gate electrode 103 as hot electrons. As shown in FIG. 3, the floating gate field effect transistor during the write operation may be considered to be a high threshold voltage floating gate field effect transistor having a high threshold voltage of about 5-6V.
The read out operation of the floating gate field effect transistor will be described with reference to FIG. 2C. the source voltage Vs of the source region 106 is fixed at the ground voltage. The drain voltage Vd of the drain region 107 is fixed at a predetermined positive voltage. The substrate voltage VB of the substrate 101 is fixed at the ground voltage. The control gate voltage Vg which has an intermediate level between the low and high levels shown in FIG. 3 is applied to the control gate electrode 105, whereby if the floating gate electrode 103 has been charged positively, then the floating gate field effect transistor turns ON, whilst if the floating gate electrode 103 has been charged negatively, then the floating gate field effect transistor turns OFF. As a result, binary digit data xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d are read out.
In accordance with the conventional floating gate field effect transistor, after either the erasure operation or the write operation has been carried out, the threshold voltage to the control gate electrode is positive. Namely, the floating gate field effect transistor is designed to be of enhancement type after either the erasure or write operation has been carried out.
If the floating gate field effect transistor becomes enhancement type in the erasure state, then this makes it difficult to reduce an ON resistance of the floating gate field effect transistor. Particularly, the semiconductor memory device having the floating gate field effect transistor needs enhancement driving ability of the floating gate field transistor and reduced ON resistance. The above conventional floating gate field effect transistor is inapplicable to the semiconductor memory device that needs enhanced driving ability and reduced ON resistance.
In the above circumstances, it had been required to develop a novel floating gate field effect transistor free from the above problem.
Accordingly, it is an object of the present invention to provide a novel floating gate field effect transistor free from the above problems.
It is a further object of the present invention to provide a novel floating gate field effect transistor suitable for application to an advanced semiconductor memory device.
It is further more object of the present invention to provide a novel floating gate field effect transistor suitable for application to an advanced logic semiconductor device.
It is a still further object of the present invention to provide a novel floating gate field effect transistor improved in driving ability thereof.
It is yet a further object of the present invention to provide a novel floating gate field effect transistor reduced in ON-resistance thereof.
It is another object of the present invention to provide a novel floating gate field effect transistor improved in holding time for holding charges in the floating gate thereof.
It is still another object of the present invention to provide a novel floating gate field effect transistor improved in acceptable cyclic numbers of writing and erasing operations.
The present invention provides a floating gate field effect transistor having a floating gate electrode and a control gate electrode, wherein a low impurity concentration layer of a first conductivity type extends between source and drain regions and in an upper region of a semiconductor region of the first conductivity type, and the low impurity concentration layer is lower in impurity concentration than the semiconductor region, and a channel region is formed in the low impurity concentration layer when the floating gate field effect transistor turns ON.
The present invention also provides a method of driving a floating gate field effect transistor having a floating gate electrode and a control gate electrode, wherein the floating gate field effect transistor is placed in a depletion type state for discharging electrons from the floating gate electrode, wherein the floating gate field effect transistor is applied with a back-bias for carrying out a read-out operation, and wherein the floating gate field effect transistor is placed in a depletion type state during a neutral state free of either electron discharge from the floating gate electrode or electron injection into the floating gate electrode.